The traditional architecture of GPS

　　GPS chipsets for commercial use are generally composed of antennas, low noise amplifiers, front-end filters, RF IC, crystal oscillator, memory chip and fundamental frequency IC(with central processing unit). As shown in Figure 2, the main function of RF IC is to reduce the 1.57542GHz carrier frequency of GPS to the fundamental frequency, which is mainly composed of low noise amplifier, mixer, automatic gain control, phase-locked loop, and analog/digital converter. General such chip design will use Bi-CMOS process to Bipolar fast, high gain, high driving force, low broadband noise and CMOS low power and high density benefits. Most of the fundamental frequency signal processing ics are made of CMOS. In addition to de-spread correlators, the general fundamental frequency signal processing chips also contain a central processing unit to process tracking and navigation algorithms to achieve satellite signal tracking and geometric positioning calculation. The CENTRAL PROCESSING UNIT IS ALSO RESPONSIBLE FOR ADDRESS/DATA OPERATIONS WITH THE MEMORY CHIP AND INTERFACE WITH EXTERNAL I/O SUCH AS UART.

　　Such traditional architectures have some bottlenecks and cannot be applied to consumer electronics such as mobile phones. The first and most critical issue is that of receptive sensitivity. General consumers in the use of GPS, most will be in the urban area, even in the building, such an environment is absolutely the enemy of GPS, because in such an environment, the signal transmitted down the satellite will not only be attenuated, multi-path reflection (multi-path), or even completely can not receive any signal (indoor). In order to improve the receiving sensitivity of the problem, manufacturers are trying to improve the RF IC and tracking navigation algorithms. Even more manufacturers and mobile communication networks (such as GSM/GPRS or WiFi hotspots) combined to provide auxiliary navigation functions, so that even if the GPS receiver is indoors, still can be located.

　　The second bottleneck is excessive power consumption. In the handheld electronic products, saving electricity has always been a most important topic. At present, the power consumption of each IC in the market varies from 150mW to 200mW. In addition to the basic power consumption needs to continue to reduce, effective power management design has also become one of the important design. In particular, the traditional architecture needs to use a CPU so that the power problem has not been improved. The chip design also reduces the voltage to 1.8V to reduce power consumption.

　　The third obstacle is the size of the GPS receiver. General GPS receiver design, generally contains the RF chip, GPS ASIC processor chip, CPU and memory. In addition to the periphery of other circuits, its size is slightly smaller than the general business card. This size, however, is not at all suitable for handheld electronics. The last one is cost. Any product to be popular with the consumer population must be competitive in price. The total BOM cost for a conventional solution is at least $15 or more.

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The basic principle of GPS navigation system is briefly introduced