1.1 RF front-end

　　The main function of the RF front-end is to down convert the RF signals received by the antenna, amplify these weak signals, convert the output signals into digital forms, and process them in programmable digital signal processors, such as DSP, FPGA and PC.

　　The RF front-end design scheme in this paper is completed with MAX2769 chip. Because it is integrated with a complete receiver link, it can achieve the reception and processing of GPS, Beidou, Galileo and other satellite signals with only a few peripheral components, and build a complete low-cost receiver scheme. The chip is integrated with dual channel low noise amplifier (LNA), temperature compensated crystal oscillator (TCXO), mixer (MIXER), baseband programmable gain amplifier (PGA), suppression image filter (IRF) Σ-Δ Fractional N frequency divider frequency synthesizer (VCO), with a total noise figure as low as 1.4dB. The integrated ADC can output 1 or 2 bit digital IF signals for I and Q channels respectively, or output three quantization bits for I branch.

　　1.2 Signal acquisition unit

　　The FPGA adopts the Cyclone IV series EP4CE115F chip produced by Altera, which has a data transmission rate of 3.125Gbps, 114,480 logic units (LE), 234K bit RAM, and up to 360 embedded 18 × 18 Multipliers, 532 user I O ports, and abundant resources.

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